For the design of digital circuits on the scale of VLSI (very large scale integration) technology, designers often employ computer aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aide in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist which is specific to a particular vendor's technology/architecture.
One operation which is often desirable in this process is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as “floor planning.” A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks,” and then reassigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block, and the placement and the routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
FIGS. 1A and 1B illustrate two methods in the prior art for performing floor planning in designing an integrated circuit. FIG. 1A illustrates a method in which floor planning is performed after a completed synthesis from HDL code. The method 10 of FIG. 1A begins an operation 12 in which an HDL code for a particular integrated circuit design is prepared; no attempt at floor planning is made when writing the source code. In operation 14, the HDL code is compiled to generate an RTL netlist. In operation 16, logic optimization is performed on the RTL netlist. This optimization typically involves substituting different gate types or combining or eliminating gates or interconnections, and often results in reordering the hierarchies and relationships between the original RTL objects and the underlying source code that produced the RTL objects. In operation 18, the optimized RTL netlist is mapped to a selected target architecture to generate a technology specific netlist. Floor planning occurs in operation 20 after operation 18 by specifying specific portions of the technology specific netlist and assigning these portions to specific portions of the integrate circuit. After floor planning in operation 20, conventional place and route software tools may be used in each area to create circuitry implemented in the vendor's target technology.
FIG. 1B shows a method 25 which involves floor planning before HDL compilation. In this case, HDL code for two regions of an integrated circuit is separately prepared along with an interconnect HDL code as shown in operations 26, 28, and 30. Then in operation 32, there is a second synthesis for each region and for the interconnect. Then place and route software tools may be used within each region to create circuitry in each region as indicated in operation 34.
The method shown in FIG. 1A can improve the placement and routing processes, but this method typically prevents the use of operation 16 or at least seriously impacts the logic optimization process. Also, floor planning after synthesis as in the case of FIG. 1A, is considerably more difficult because the understanding of a design has deteriorated due to the loss of the contextual information from the HDL code which has been hidden within the design's programmable logic cells and the level of detail has increased dramatically.
In the case of the method of FIG. 1B, the placement information can be used by the synthesis tool to make logic optimization decisions. Unfortunately, it is not easy to know whether the capacity of a block has been overflowed or which logic has the most critical timing impact. In addition, the design's granularity prevents manipulation of lower level functions such as counters, adders, state machines, etc.
From the foregoing it can be seen that it is desirable to provide an improved method for designing an integrated circuit.